In this tools paper, we present the Anonymous Cache and Virtual Memory Simulators, which are designed to assist in the teaching and learning of these subtopics of the memory hierarchy found in computer organization, computer architecture, and operating systems courses. These topics can be difficult to teach due to the significant amount of terminology and interacting design parameters and policies found in the processes of address translation and data fetching. These interactive, web-based simulators let users observe the processes and study the fundamental concepts and policies of caching and virtual memory. They aim to improve functionality and usability by (1) allowing for a wider range of parameters, policies, and operations, (2) providing detailed explanations of process steps, (3) highlighting system changes, (4) showing data values in memory, and (5) allowing users to navigate the operation history.

We present the major features of these simulators along with their integration in our computer organization course and other possible use cases. Student survey results from three recent offerings of this course reveal that the majority of students agree that the simulators were easy to use and beneficial to their learning of caching and virtual memory topics. However, due to differences in integration, the cache simulator was used by significantly more students than the virtual memory simulator. The provided suggestions, including tutorials and user interface tweaks (display and inputs), will inform future improvements. The source code for the simulators is available for others to use, modify, and extend.

Associate Teaching Professor in the Paul G. Allen School of Computer Science & Engineering (CSE) at the University of Washington, Seattle (UW). I primarily teach computer engineering courses (e.g., digital logic design, computer organization, systems programming) and am passionate about teacher training, particularly for post-secondary teaching-track roles (e.g., TA training, students as instructors of record, teaching-track mentoring).