The RISC-V computer architecture has generated a lot of inter- est within computer science communities and has seen increased usage in recent years with companies like NVIDIA, Huawei, and Google having either announced or begun to produce hardware incorporating the RISC-V architecture. Because of this popularity, Embedded Xinu, a simple, education focused operating system, was ported to RISC-V. While Embedded Xinu was successfully ported to RISC-V, due to limitations in RISC-V boot loader technology, the kernel was required to break privilege level specifications and con- figure the hardware directly from machine mode. To remedy this the kernel and boot sequence needed modifications to run exclu- sively in supervisor mode, as intended in the RISC-V specifications. These modifications allow for proper hands on instruction regard- ing privilege levels and user-kernel space distinctions, improving the education breadth and quality of operating systems instruction using Embedded Xinu